The present invention generally relates to a method for testing circuit modules, and in particular relates to a method for testing circuit modules which is used in a test device for sampling testing.
Testing of integrated circuits (ICs) and other assemblies is acquiring ever greater importance against the background of increasing miniaturization. By way of example, microprocessors are highly complex ICs which must be tested exactly for malfunctions, in particular for a use in central processing units (CPUs). However, there are numerous further applications for sampling testing of electronic circuit modules.
Circuit modules are constructed, for example, from scan chains which are provided by a series of logical functional units such as e.g. gate units and/or flip-flop units. These scan chains are conventionally tested by applying sampling vectors, which are constructed from a bit pattern sequence of logic “ones” and logic “zeros”, to an input of a circuit module to be tested, and then, at an output, comparing the resulting sampling vectors with an expected result, for example with a desired sampling vector.
In this case, sampling vectors which are fed to an input of a circuit module to be tested are provided as sampling input signals, while resulting sampling vectors which are output by an output of the circuit module to be tested are compared as sampling output signals with expected result sampling vectors, which are referred to as desired sampling output signals, in a comparator unit.
In the testing of circuit modules, a test device is conventionally set up for sampling testing, in which case a test quality must be maintained even in the event of the test requirement being extended.
With the aid of a so-called ATPG software (Automated Test Pattern Generation software), specific digital test signals for testing circuit modules, which may be designed for example as “channel modules” or as “control modules”, are generated by a test pattern generator. These test signals, which are prescribed as an arbitrary bit pattern sequence (e.g. 0-1-0-0-1-1-0-1- . . . ) in the form of sampling vectors, are fed to the circuit modules to be tested.
The terms “channel module” and “control module” hereinafter merely designate different circuit modules. Here, the term channel module designates a circuit module which generally occurs multiply, but at least once, in a circuit and in which case individual channel modules are each identical. And here, the term control module designates a circuit module which occurs multiply, but at least once, in a circuit and in which case once again individual control modules are each identical.
FIG. 1 shows a test device for channel modules 101a, . . . 101i, . . . 101d arranged in parallel according to the prior art. A first terminal unit 401 is connected to a control module 102, in which case signals can be exchanged between the first terminal unit 401 and the control module 102 in both directions as sampling input signals and sampling output signals. By way of example, FIG. 1 illustrates four channel modules 101a, 101b, 101c and 101d which are tested in a parallel manner. The channel modules 101a-101d are each connected to the control module 102 and a second terminal unit 402, in which case channel sampling input signals and channel sampling output signals can each be exchanged between the channel modules 101a-101d and the control module 102 or the second terminal unit 402.
The circuit modules present in a circuit, in this case designated as “channel modules” or as “control modules”, comprise scan chains, e.g. for a channel module 101a the scan chains A31-A3N, which are formed for example by a series of flip-flop units, where N denotes the total number of scan chains in the channel module 101a. 
In this case, the sampling signals (sampling input signal and sampling output signal) which are generated in a test generator 112 are used to test a number of N scan chains (A31-AN) of which the respective circuit modules are composed. Test methods according to the prior art are based on a use of sampling input signals which have to be present, and also stored, separately for each circuit module (in this case channel modules and control modules). The respective sampling output signals are fed to a comparator unit 113 in which the respective sampling output signals are compared with desired sampling output signals, and a test result is thus obtained.
In order to provide sampling input signals in the event of circuits being extended by individual circuit modules, a memory extension of the test device is disadvantageously required in the case of test devices for sampling testing according to the prior art. However, if such a memory extension cannot be provided, sampling signals must necessarily be reduced, which leads to a disadvantage of a reduced test quality.